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September 16, 2014

Comments

Mike Murphy

Tiering? Exactly. I mean we've been doing tiering for decades, with L1, L2 L3 SRAM moving from separate external chips to on-board the CPU. And SAN cache on the front-end has somehow now become flash in a lot of cases. I suspect we will see TLC and MLC NAND get moved to lower tiers with SAS connections, while DRAM and PCM become upper tiers being served out of PCIe and RDMA on the memory controller bus.

Also, I keep asking myself why we are still calling this stuff storage. At some point, the definition may change. I mean so much data in flight with all that movement and intelligence seems to remind me of a smart application, a server, whatever. Isn't storage a place where you put something that doesn't really move all that often?

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Chuck Hollis


  • Chuck Hollis
    SVP, Oracle Converged Infrastructure Systems
    @chuckhollis

    Chuck now works for Oracle, and is now deeply embroiled in IT infrastructure.

    Previously, he was with VMware for 2 years, and EMC for 18 years before that, most of them great.

    He enjoys speaking to customer and industry audiences about a variety of technology topics, and -- of course -- enjoys blogging.

    Chuck lives in Vero Beach, FL with his wife and four dogs when he's not traveling. In his spare time, Chuck is working on his second career as an aging rock musician.

    Warning: do not ever buy him a drink when there is a piano nearby.

    Note: these are my personal views, and aren't reviewed or approved by my employer.
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